MN6761S
Pin Descriptions (continued)
Pin No.
16
Symbol
VR
Pin Name
Vertical reset output
For Video Equipment
Function Description
This pin generates a vertical reset pulse for the
V-SERATION interval detected in the GLSYNC signal.
Connect it to the VR pin of the synchronizing signal
generator.
25
SCPCO
Subcarrier phase
comparator output
This pin is at "L" level when the SC1 signal leads the
GLBSC signal and is at "H" level when the signal lags.
At all other times, it is in the high-impedance state.
Clock oscillator pins for the subcarrier circuits.
Connect these pins to a crystal oscillator, capacitor, and
variable capacitor. (The pins have built-in feedback resistors.)
The circuit oscillates during external synchronization mode.
The oscillation stops for internal synchronization mode.
The oscillator frequency, 4f
SC
, is 14.31818 MHz for NTSC
and 14.734 MHz for PAL.
26
4f
SC
OSCI
Oscillator input for
subcarrier circuits
27
4f
SC
OSCO
Oscillator output for
subcarrier circuits
28
4f
SC
Subcarrier clock output
Clock output from subcarrier circuits.
In external synchronization mode, this pin provides the
(4f
SC
) clock signal; in internal synchronization mode, it
remains at "L" level. Connect this pin to the EX4f
SC
I pin on
the synchronizing signal generator.
18
LSWCONT
Line switch polarity
control output
During PAL operation, this pin emits an error detection
pulse if the LSW polarity is wrong, and the chip reverses
the LSW polarity. During internal synchronization mode,
this pin remains at "L" level. Connect this pin to the
LSWCONT pin on the synchronizing signal generator.
19
EXT/INT
Automatic internal/
external switching
output
If the chip detects GLSYNC input, it switches to external
synchronization mode and drives this pin at "H" level.
Otherwise, it switches to internal synchronization mode and
drives this pin at "L" level. Connect this pin to the EXT/INT
pin on the synchronizing signal generator.
5
BGP
Burst gate pulse output
These pulses have a width of 2.5 µs (NTSC) or 2.3 µs
(PAL) and trail the rising edge of the HSYNC signal by
5.3 µs (NTSC) or 5.6 µs.
They are generated for only 10 H to 256 H (NTSC) or
304 H (PAL) after the VR pulse.
20
21
10
HBLK
TEST1
TEST2
Horizontal blanking
output
Test inputs
These pulses have a width of 8.9 µs (NTSC) or 8.8 µs
(PAL) and follow the rising edge of the HSYNC signal.
Leave these test inputs open. (The pins include built-in
pull-up resistors.)
PANASONIC [ PANASONIC SEMICONDUCTOR ]
