MN6761S
3. Subcarrier synchronization block
For Video Equipment
This block converts the SC1 output from the synchronizing signal generator into four signals with the same
frequency as the burst subcarrier, but different phases. In this phase-locked loop circuit, the phase of GLBSC
is compared with the phase selected by 2 bits (SCPSW1 and SCPSW2).
During PAL operation, if the LSW polarity is wrong, this block sends an error detection pulse (LSWCONT)
to the synchronizing signal generator and reverses the LSW polarity. It also adjusts the relationship between
fields 1 through 4.
4. Oscillator blocks
The Xf
H
and 4f
SC
oscillator blocks operate only during external synchronization mode. Connecting a variable
capacitor creates voltage-controlled oscillators that generate the synchronization signal circuit clock (Xf
H
)
and subcarrier circuit clock (4f
SC
) for output to the synchronization signal generator.
5. Automatic internal/external switching block
If it detects a minimum of ten edges from the GLSYNC input, this block switches the chip to the external
synchronization mode and drives the EXT/INT pin at "H" level. If there are no edges in the GLSYNC input
for 10 H, this block switches the chip to the internal synchronization mode and drives this pin at "L" level.
HBLK and BGP plus generator
GLSYNC
HBLK
BGP
5.3µs (NTSC)
5.6µs (PAL)
2.5µs (NTSC)
2.3µs (PAL)
8.9µs (NTSC)
8.8µs (PAL)
HBLK and BGP pulse timing chart
There is an HBLK pulse for each H.
BGP pulses are generated for only 10 H to 256 H (NTSC) or 304 H (PAL) after the VR pulse.
PANASONIC [ PANASONIC SEMICONDUCTOR ]
