AN5394FB
ICs for TV
■ Application Note (continued)
2. I2C bus control contents (continued)
5) V-latch operation
(Function) The data for sub-address 00 to 03 remains unchanged until VP pulse comes.
Data 1
transfer
Data 2
transfer
I2C bus
VP
Old data
Data 1
Data 2
IC ouput
6) Auto increment: This IC performs the designation of sub address by using the lower 5 bits. The uppermost bit is
used for designation of auto increment.
• When the sub address uppermost bit is defined as 0 (sub address: 00 to 19 HEX)
The sequential data transfer leads to the sequential change of sub address, then the data is inputted.
I2C bus
transfer
Sub address
X
Slave
address
Data
1
Data
2
Data
3
Sub address
X
Input data
Data 1
X + 1
Data 2
X + 2
Data 3
The data is inputted as above. But the data will be invalid after sub address 1A.
• When the sub address uppermost bit is defined as 1 or sub address is 80 to 99 HEX, the sequential data transfer
leads to data input on the same address.
I2C bus
transfer
Slave
address
Sub address
8Y
Data
1
Data
2
Data
3
Sub address
Input data
Data 1
Data 2
8Y
8Y
8Y
Data 3
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