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AN5394FB 参数 Datasheet PDF下载

AN5394FB图片预览
型号: AN5394FB
PDF下载: 下载PDF文件 查看货源
内容描述: RGB处理器IC为HDTV (日本)和宽屏幕电视 [RGB processor IC for the HDTV(Japan) and wide-screen TV]
分类和应用: 电视
文件页数/大小: 33 页 / 236 K
品牌: PANASONIC [ PANASONIC ]
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ICs for TV  
AN5394FB  
Application Note (continued)  
2. I2C bus control contents  
1) I2C bus protocol  
S
Slave address  
O
A
Sub address  
A
Data byte  
A
P
Start condition  
Write  
Acknowledge bit  
Stop condition  
2) Slave address  
The slave address of this IC is 84H.  
3) Since the data status at power on is not guaranteed, be sure to send data to all addresses before using.  
4) Sub-address data  
DAC name  
bit Sub  
Data address(H)  
Operation  
Remarks  
address(H) ( )Standard status  
Color control  
7
7
00  
01  
00 to (40) to 7F Chroma amplitude upped with With V latch  
data upped Complete iris of Refer to "(5) V latch op-  
data(00) color with  
eration" in Application Note  
for details.  
Tint control  
00 to (40) to 7F Direction to make the flesh With V-latch  
tone red with data(00)  
Direction to make the flesh  
tone green with data(7F)  
Brightness  
control  
8
7
02  
03  
00 to (80) to FF Pedestal upped with data  
upped  
With V-latch  
Contrast control  
00 to (40) to (7F) Signal amplitude upped with With V-latch  
data upped complete iris of  
color with data(00)  
Drive (R)  
Drive (G)  
Drive (B)  
Cufoff (R)  
8
8
8
04  
05  
06  
00 to (40) to 7F R gain upped with data upped  
00 to (40) to 7F G gain upped with data upped  
00 to (40) to 7F B gain upped with data upped  
8
+
07  
+
(00) to 80 to FF  
Cutoff (R)  
2SW  
0A  
00 to (80) to C0  
R-out pedestal is  
upped with data up  
30LSB  
30LSB  
30LSB  
2.0 V  
07 00  
0A 00  
FF 00  
FF 00  
80  
FF 00  
FF  
40  
C0  
25  
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