PAM8803
3W Filterless Stereo Class-D Audio Amplifier
with Digital Volume Control
Application Information
Maximum Gain
There are 64 discrete gain settings ranging from
+24dB maximum to -75dB minimum. Upon device
As shown in block diagram(page 2),the PAM8803
has two internal amplifiers stage. The first
stage's gain is externally configurable, while the
second stage's is internally fixed in a fixed-gain,
inverting configuration. The closed-loop gain of
the first stage is set by selecting the ratio of Rf to
Ri while the second stage's gain is fixed at 2x.
Consequently, the differential gain for the IC is
power on or applied a logic low to the RST pin,
the amplifier's gain is set to a default value of
2.6dB. However, when coming out of mute mode,
the PAM8803 will revert back to its previous gain
setting. Volume levels for each step vary and are
specified in Gain Setting table on page 7.
If both the UP and DN pins are held high, no
volume change will occur. Trigger points for the
UP and DN pins are at 70% of VDD minimum for a
logic high, and 20% of VDD maximum for a logic
low. It is recommended, however, to toggle UP
and DN between VD D and GND for best
performance.
AVD=20*log [2*(Rf/Ri)]
The PAM8803 sets maximum Rf=218kΩ and
minimum Ri=27kΩ, thus the maximum closed-
gain is 24dB.
Digital Volume Control (DVC)
UP/DN
The PAM8803 features a digital volume control
which consists of the UP, DN and RST pins. An
internal clock is used where the clock frequency
value is determined from the following formula:
VOLUME
LEVEL
2 cycles
9.5 cycles
3.5 cycles
2 cycles
Figure 1.Timming Diagram
Mute Operation
fCLK = fOSC / 213
The MUTE pin is an input for controlling the
output state of the PAM8803. A logic low on this
pin disables the outputs, and a logic high on this
pin enables the outputs. This pin may be used as
a quick disable or enable of the outputs without a
volume fade. Quiescent current is listed in the
electrical characteristic table. The MUTE pin can
be left floating due to the pull-up internal.
The oscillator frequency fOSC value is 200kHz
typical,with 20% tolerance.The DVC’s clock
frequency is 33Hz (cycle time 30ms) typical.
Volume changes are then effected by toggling
either the UP or DN pins with a logic low. After a
period of 3.5 clocks pulses with either the UP or
DN pins held low, the volume will change to the
next specified step, either UP or DN, and
followed by a short delay. This delay decreases
the longer the line is held low, eventually
reaching a delay of zero. The delay allows the
user to pull the UP or DN terminal low once for
one volume change, or hold down to ramp
several volume changes. The delay is optimally
configured for push button volume control.
Shutdown operation
In order to reduce power consumption while not
in use, the PAM8803 contains shutdown circuitry
that is used to turn off the amplifier's bias
circuitry. This shutdown feature turns the
amplifier off when logic low is placed on the
SHDN pin. By switching the SHDN pin connected
to GND, the PAM8803 supply current draw will be
minimized in idle mode. The SHDN pin cannot be
left floating due to the pull-down internal.
If either the UP or DN pin remains low after the
first volume transition the volume will change
again, but this time after 9.5 clock pulses. The
followed transition occurs at 2 clock pulses for
each volume transition. This is intended to
provide the user with a volume control that
pauses briefly after initial application, and then
slowly increases the rate of volume change as it
is continuously applied. This cycle is shown in
the timing diagram shown in figure 1.
Power Analog Microelectronics,Inc
www.poweranalog.com
12/2009 Rev 1.4
9
PAM [ POWER ANALOG MICOELECTRONICS ]
