PAM2303
3A Low Noise Step-Down DC-DC Converter
Block Diagram
VIN
+
IAMP
-
PVIN
1.5M
OSC
SLOPE
COMP
FB
FREQ
SHIFT
MAIN
SWITCH(PCH)
OSC
S Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
R1
R2
R Q
RS LATCH
ANTI-
SHOOT-
THRU
-
+
SW
EA
VIN
COMP
SYNCHRONOUS
RECTIFIER(NCH)
0.6VREF
EN
+
IRCMP
-
SHUTDOWN
PGND
GND
TEST
Pin Configuration & Marking Information
Top View
QFN 3X3-16
Top View
SOP-8(EP)
8
7
6
5
16 15 14 13
A/B: Pin Configuration
Y: Year
W: Week
PVIN
12
PGND
PGND
PGND
FB
1
2
3
4
P2303A
XXXYW
11 PVIN
10 PVIN
P2303B
XXXYW
X: Internal Code
9
VIN
5
6
7
8
1
2
3
4
Pin Description
Name
PGND
FB
QFN3X3-16 SOP-8(EP)
Function
1,2,3
4
2
3
4
-
Main power ground pin
Feedback voltage to internal error amplifier, the threshold voltage is 0.6V.
Signal ground for small signal components.
GND
NC
5
6,16
No connected
Enable control input. Force this pin voltage above 1.5V, enables the chip,
and below 0.3V shuts down the device.
EN
7
5
Test
VIN
8
6
7
8
1
Test mode. “Low” connection is recommended.
Bias supply. Chip main power supply pin
9
PVIN
SW
10,11,12
13,14,15
Input supply for power stage. Must be closely decoupled to PGND
The drains of the internal main and synchronous power MOSFET.
Power Analog Microelectronics, Inc
www.poweranalog.com
11/2011 Rev1.2
2
PAM [ POWER ANALOG MICOELECTRONICS ]
