OXCB950
OXFORD SEMICONDUCTOR LTD.
5 CONFIGURATION & OPERATION
The OXCB950 is configured by system start-up software
during the bootstrap process that follows bus reset.
the assigned addresses in the usual fashion, with the
improved data throughput provided by cardbus/PCI buses.
By default, the device powers-up in the cardbus mode and
in this mode, the system examines the Cardbus CIS
pointer value contained in the predefined PCI Header
region (at Dword 0Ahex) to locate the start of the Cardbus
A set of local configuration registers have been provided
that can be used to control the device’s characteristics
(such as interrupt handling) and report internal functional
status. This is on top of the UART registers and the
registers contained in both the PCI configuration Space
and the Cardbus Information Structure (CIS). These local
registers can be set up by device drivers or from the
optional EEPROM.
Information Structure (CIS). It then traverses the tuple
NOTE1
information contained in this CIS area
to identify the
device type and the necessary resources requested by the
device.
For the PCI application mode, whereby the device’s default
cardbus mode is overridden into the PCI mode though the
use of the optional EEPROM (this takes place prior to any
configuration accesses), the system scans the PCI bus and
reads the vendor and device identification codes from any
devices it finds and the resources being requested.
The EEPROM can also be used to redefine the reset
values of most register areas to tailor the device to the end
users requirements if the default values do not meet the
specific requirements of the manufacturer, such as the
identification registers. As an additional enhancement, the
EEPROM can be used to pre-program the UART, allowing
pre-configuration, without requiring device driver changes.
This allows the enhanced features of the integrated UART
to be in place prior to handover to any generic device
drivers.
For both cardbus and PCI applications, the system then
loads the device-driver software according to this
information and configures the I/O, memory and interrupt
resources. Device drivers can then access the functions at
NOTE1
Windows Support for Cardbus applications, treats the information contained in the CIS area as “supplemental” information
for devices that are not fully described using the PCI configuration Space. This means that it is possible that provided the PCI
header space implements the minimum fields as recommended by Microsoft (the cardbus “Allocated” and “Reserved” fields are
defined) then Windows will not utilise the information contained in the CIS.
DS-0033 Sep 05
External-Free Release
Page 12
OXFORD [ OXFORD SEMICONDUCTOR ]
