OXFORD SEMICONDUCTOR LTD.
OX16PCI958 DATA SHEET
3.2.
Configuration & Control Registers
Table 6 summarizes the configuration and control registers for quick reference.
Table 6 Configuration & Control Register Summary
A
30h
use
EEPROM-
control register
Power-
management
control register
UART interrupt
status (RO)
UART-enable
register
SISR enable
UART
configuration
Global pre-
divider
RFU1
D7
EET2
D6
EET1
D5
RFU
D4
EEDIO
data in
D3
EECS
D2
EECK
D1
EEDIO
output
enable
PM_OSC
U2INT
U2EN
U1INT
U1EN
U0INT
U0EN
D0
EEDIO
data out
31h
34h
40h
42h
4Ch
50h
RFU
U7INT
U7EN
SEN
RFU
RFU1
U6INT
U6EN
PM_DRIVER
U5INT
U5EN
U4INT
U4EN
PM_LCLK
U3INT
U3EN
RFU
1b
GCS1
RFU1
RFU
RFU
GCS0
RFU1
RFU
EEPROM-Control Register
The OX16PCI958 automatically takes control of the EECS, EECK and EEDIO pins after a deassertion
of the host bus RESET signal, in order to read in configuration data. Afterwards, the signals may be
controlled though accesses to this register.
Field (Bits)
EET2 (7)
Description
High—at least 70 PCI clock cycles have occurred since the register was last written.
Cleared when the register is written. Set to the value of EET1 every 70th PCI clock cycle.
This may be useful for ensuring that EEPROM timing constraints are met
Cleared when the register is written. Set every 70th PCI clock cycle
Returns the current logic level on the EEDIO pin.
Controls EECS output.
Controls EECK output
1—the value last written to bit 0 is driven on the EEDIO pin
0—EEDIO pin is tri-stated
Controls the logic level driven onto EEDIO when bit 1 is set.
EET1 (6)
EEDIO data in (4)
EECS (3)
EECK (2)
EEDIO output
enable (1)
EEDIO data out (0)
This register is set to 00h on a PCI reset.
DS-0022 Nov 05
External—Free Release
Page 9
OXFORD [ OXFORD SEMICONDUCTOR ]
