OX16PCI958 DATA SHEET
OXFORD SEMICONDUCTOR LTD.
Base Address Register 4
Interrupt Pin Register
This base address register is for a mapping of
64 bytes in 32-bit memory space (non-
prefetchable memory). Accesses made to the
memory range defined by this BAR map to
internal UARTs at internal addresses 80h-BFh.
This register is read-only via configuration
accesses, but may be set to either 00h or 01h
using local-register access via BAR0, BAR1 or
EEPROM configuration. It is set to 01h
following a PCI reset.
Base Address Register 5
Interrupt Line Register
This base address register is for a mapping of
16 bytes in 32-bit memory space (non-
prefetchable memory). Accesses made to the
memory range defined by this BAR map to
internal addresses C0h-CFh.
This register is read-write accessible via
configuration accesses. It is set to 00h
following a PCI reset.
Power-Management Registers
Cardbus CIS Pointer
The Power Management Capabilities register
is read-only via configuration accesses. It
provides the host system with information on
the power-management capabilities of the PCI
device and returns the current value of the
PMC register. It is set to a generic-configured
value following a PCI reset.
Hard-wired to zero, as this device is not for
use in CardBus applications.
Subsystem Device ID Register
This register is mostly just for the passing of
power management information to the host
system, but two of the fields also have an
affect on the operation of the block:
This register is read-only via configuration
accesses, and returns the current value of the
SDID register.
Subsystem Vendor ID register
Bits Description
10
0—writing 10b to the PowerState bits in
PMCSR (see below) leaves PowerState
unchanged
This register is read-only via configuration
accesses, and returns the current value of the
SVID register.
9
0—writing 01b to the PowerState bits in
the PMCSR (see below) leaves
PowerState unchanged
Expansion ROM Base Address Register
Hard-wired to zero.
Capabilities Pointer
This register is read-only and always returns
40h, as this is where the power management
registers are located.
Max_lat Register
Read-only register which always returns 00h.
(Not relevant for target-only PCI devices)
Min_gnt Register
Read-only register which always returns 00h.
(Not relevant for target-only PCI devices)
DS-0022 Nov 05
External—Free Release
Page 13
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