OX12PCI840-PQAG 参数 Datasheet PDF下载

OXFORD SEMICONDUCTOR LTD.

OX12PCI840

C

ONTENTS

1

2

3

4

4.1

4.2

4.2.1

4.3

4.3.1

4.4

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

4.5

4.6

4.6.1

PIN INFORMATION ............................................................................................................................... 4

PIN DESCRIPTIONS.............................................................................................................................. 5

CONFIGURATION & OPERATION ....................................................................................................... 8

PCI TARGET CONTROLLER................................................................................................................ 9

OPERATION ....................................................................................................................................................................... 9

CONFIGURATION SPACE ................................................................................................................................................. 9

PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 10

ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 11

PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 11

ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 12

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 12

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 13

LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 13

LOCAL BUS TIMING PARAMETER/BAR SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C): ............................................ 14

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X10)................................................ 15

PCI INTERRUPTS............................................................................................................................................................. 16

POWER MANAGEMENT .................................................................................................................................................. 17

POWER MANAGEMENT USING MIO.......................................................................................................................... 17

5

BI-DIRECTIONAL PARALLEL PORT ................................................................................................. 18

5.1

OPERATION AND MODE SELECTION ........................................................................................................................... 18

5.1.1

SPP MODE ................................................................................................................................................................... 18

5.1.2

PS2 MODE.................................................................................................................................................................... 18

5.1.3

EPP MODE ................................................................................................................................................................... 18

5.1.4

ECP MODE ................................................................................................................................................................... 18

5.2

PARALLEL PORT INTERRUPT ....................................................................................................................................... 18

5.3

REGISTER DESCRIPTION............................................................................................................................................... 19

5.3.1

PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 19

5.3.2

ECP FIFO ADDRESS / RLE ......................................................................................................................................... 19

5.3.3

DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 19

5.3.4

DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 20

5.3.5

EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 20

5.3.6

EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 20

5.3.7

ECP DATA FIFO ........................................................................................................................................................... 20

5.3.8

TEST FIFO .................................................................................................................................................................... 20

5.3.9

CONFIGURATION A REGISTER ................................................................................................................................. 20

5.3.10

CONFIGURATION B REGISTER ................................................................................................................................. 21

5.3.11

EXTENDED CONTROL REGISTER ‘ECR’................................................................................................................... 21

6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

SERIAL EEPROM................................................................................................................................ 22

SPECIFICATION ............................................................................................................................................................... 22

EEPROM DATA ORGANISATION ................................................................................................................................... 22

ZONE0: HEADER ......................................................................................................................................................... 22

ZONE1: LOCAL CONFIGURATION REGISTERS........................................................................................................ 23

ZONE2: IDENTIFICATION REGISTERS ...................................................................................................................... 23

ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................. 23

ZONE4: FUNCTION ACCESS ...................................................................................................................................... 25

7

8

8.1

OPERATING CONDITIONS................................................................................................................. 26

DC ELECTRICAL CHARACTERISTICS ............................................................................................. 26

Page 2

NON-PCI I/O BUFFERS.................................................................................................................................................... 26

DS-0021 Jun 05