UC3842B, UC3843B, UC2842B, UC2843B
OPERATING DESCRIPTION
The UC3842B, UC3843B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost−effective
solution with minimal external components. A
representative block diagram is shown in Figure 19.
Oscillator
ln
D
max
+
ln
V
V
*V
ref
RT CT(valley)
V
*V
ref
RT CT(peak)
*V
ref
RT CT(valley)
V
*V
ref
RT CT(peak)
@
R
R I
)V
*V
T dischg
ref
RT CT(peak)
I dischg
)V
*V
T
ref
RT CT(valley)
(eq. 4)
The oscillator frequency is programmed by the values
chosen for the timing components R
T
and C
T.
It must also be
noted that the value of R
T
uniquely determines the
maximum duty ratio of UC384xx. The oscillator
configuration depicting the connection of the timing
components to the R
T
/C
T
pin of the controller is shown in
Figure 18. Capacitor C
T
gets charged from the V
ref
source,
through resistor R
T
to its peak threshold V
RT/CT(peak)
,
typically 2.8 V. Upon reaching this peak threshold volage, an
internal 8.3 mA current source, I
dischg
, is enabled and the
voltage across C
T
begins to decrease. Once the voltage
across C
T
reaches its valley threshold, V
RT/CT(valley)
,
typically 1.2 V, I
dischg
turns off. This allows capacitor C
T
to
charge up again from V
ref
. This entire cycle repeats, and the
resulting waveform on the R
T
/C
T
pin has a sawtooth shape.
Typical waveforms are shown in Figure 20.
The oscillator thresholds are temperature compensated to
within
±6%
at 50 kHz
.
Considering the general industry
trend of operating switching controllers at higher
frequencies, the UC384xx is guaranteed to operate within
±10%
at 250 kHz
.
These internal circuit refinements
minimize variations of oscillator frequency and maximum
duty ratio.
The charging and discharging times of the timing
capacitor C
T
are calculated using Equations 1 and 2. These
equations do not take into account the propagation delays of
the internal comparator. Hence, at higher frequencies, the
calculated value of the oscillator frequency differs from the
actual value.
t
RT
CT(chg)
Clearly, the maximum duty ratio is determined by the
timing resistor R
T
. Therefore, R
T
is chosen such as to
achieve a desired maximum duty ratio. Once R
T
has been
selected, C
T
can now be chosen to obtain the desired
switching frequency as per Equation 5.
f
+
R
T
C
T
ln
1
V
*V
ref
RT CT(valley)
V
*V
ref
RT CT(peak)
@
R
R I
)V
*V
T dischg
ref
RT CT(peak)
I dischg
)V
*V
T
ref
RT CT(valley)
(eq. 5)
Figure 2 shows the frequency and maximum duty ratio
variation versus R
T
for given values of C
T
. Care should be
taken to ensure that the absolute minimum value of R
T
should not be less than 542
W.
However, considering a 10%
tolerance for the timing resistor, the nearest available
standard resistor of 680
W
is the absolute minimum that can
be used to guarantee normal oscillator operation. If a timing
resistor smaller than this value is used, then the charging
current through the R
T
, C
T
path will exceed the pulldown
(discharge) current and the oscillator will get permanently
locked/latched to an undefined state.
In many noise-sensitive applications it may be desirable
to frequency-lock the converter to an external system clock.
This can be accomplished by applying a clock signal to
the
circuit shown in Figure 22. For reliable synchronization, the
free-running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi-unit
synchronization is shown in Figure 23. By tailoring the
clock waveform, accurate Output duty ratio clamping can be
achieved.
V
ref
R
T
R
T
/C
T
I
dischg
2.8 V
1.2 V
Enable
C
T
+
R
T
C
T
ln
V
RT
V
RT
CT(valley)
*
V
ref
CT(peak)
*
V
ref
CT(peak)
CT(valley)
(eq. 1)
t
RT
CT(dischg)
+
R
T
C
T
ln
R
T
I
dischg
)
V
RT
R
T
I
dischg
)
V
RT
*
V
ref
*
V
ref
(eq. 2)
The maximum duty ratio,
D
max
is given by Equation 3.
D
max
+
t
RT
t
RT CT(chg)
CT(chg)
)
t
RT CT(dischg)
(eq. 3)
Figure 18. Oscillator Configuration
Substituting Equations 1 and 2 into Equation 3, and after
algebraic simplification, we obtain
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