UC3842A, UC3843A, UC2842A, UC2843A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards.
High Frequency
circuit layout techniques are imperative to prevent pulse
width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1
mF)
connected directly to V
CC
, V
C
,
and V
ref
may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed−loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t
0
, switch
conduction begins, causing the inductor current to rise at a
slope of m
1
. This slope is a function of the input voltage
divided by the inductance. At t
1
, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m
2
until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small
DI
(dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t
2
) is increased
by
DI
+
DI
m2/m1. The minimum current at the next cycle
(t
3
) decreases to (DI +
D
I m
2
/m
1
) (m
2
/m
1
). This perturbation
is multiplied by m
2
.m
1
on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m
2
/m
1
is greater than 1, the converter
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the
DI
perturbation will decrease to zero
on succeeding cycles. This compensation ramp (m
3
) must
have a slope equal to or slightly greater than m
2
/2 for
stability. With m
2
/2 slope compensation, the average
inductor current follows the control voltage yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
DI
Control Voltage
m2
m1
Inductor
Current
t
0
DI
+
DI
m
2
m
1
Oscillator Period
t
1
t
2
m
2
D
I +
DI
m
m
2
m
1
t
3
(A)
1
(B)
Control Voltage
DI
m3
m1
m2
Oscillator Period
t
4
t5
Inductor
Current
t
6
Figure 20. Continuous Current Waveforms
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