UC3842A, 43A UC2842A, 43A
Figure 20. External Clock Synchronization
Vref
8(14)
RT
R
Bias
R
Osc
0.01
CT
47
4(7)
+
–
2(3)
1(1)
5(9)
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
f=
1.44
(RA + 2RB)C
RB
Dmax =
RA + 2RB
EA
+
5.0k
5
2
2R
R
C
RA
8
RB
6
5.0k
+
–
+
–
4
8(14)
R
Bias
R
Osc
Q
S
3
7
2(3)
1(1)
To Additional
UCX84XA’s
5(9)
4(7)
+
–
EA
+
Figure 21. External Duty Cycle Clamp and
Multi Unit Synchronization
External
Sync
Input
R
5.0k
MC1455
1
2R
R
Figure 22. Adjustable Reduction of Clamp Level
VCC
7(12)
+
–
Vin
Figure 23. Soft–Start Circuit
5.0Vref
8(14)
R
Bias
R
Osc
4(7)
R2
2(3)
1(1)
5(9)
1.67
R2
+1
R1
R1 R2
R1 + R2
+
–
EA
+
1.0mA
2R
R
–
+
1.0V
R1
+
–
VClamp
S
+
–
5.0Vref
+
–
7(11)
Q1
6(10)
4(7)
+
–
2(3)
1.0M
RS
C
1(1)
tSoft–Start
EA
+
1.0mA
2R
R
S
–
+
1.0V
R
Q
Osc
8(14)
R
Bias
R
+
–
+
–
R
Comp/Latch
Q
5(8)
3(5)
3600C in
µF
5(9)
VClamp =
+ 0.33 x 10 – 3
Ipk(max) = VClamp
RS
Where: 0
≤
VClamp
≤
1.0 V
Figure 24. Adjustable Buffered Reduction of
Clamp Level with Soft–Start
VCC
7(12)
+
–
Vin
Figure 25. Current Sensing Power MOSFET
VCC
(12)
+
–
RS Ipk rDS(on)
VPin 5 =
rDM(on) + RS
If: SENSEFET = MTP10N10M
RS = 200
Then: Vpin 5 = 0.075 Ipk
D SENSEFET
Vin
S
M
K
5.0Vref
8(14)
R
Bias
R
Osc
4(7)
+
–
2(3)
R2
1(1)
C
MPSA63
R1
VClamp =
1.67
R2
+1
R1
5(9)
Ipk(max) = VClamp
RS
tSoftstart = – In
+
1.0mA
EA
2R
R
+
–
VClamp
–
+
1.0V
+
–
5.0Vref
+
–
7(11)
Q1
6(10)
+
–
+
–
+
–
(11)
(10) G
S
Q
R
Comp/Latch
5(8)
3(5)
RS
S
Q
–
R
+
Comp/Latch
(8)
(5)
Power Ground
To Input Source
Return
Control CIrcuitry
Ground:
To Pin (9)
RS
1/4 W
Where: 0
≤
VClamp
≤
1.0 V
1–
VC
3VClamp
C
R1 R2
R1 + R2
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 22 and 24.
MOTOROLA ANALOG IC DEVICE DATA
11
ONSEMI [ ON SEMICONDUCTOR ]
