SN74LS373 SN74LS374
CONNECTION DIAGRAM DIP
(TOP VIEW)
SN74LS373
V
CC
20
O
7
19
D
7
18
D
6
17
O
6
16
O
5
15
D
5
14
D
4
13
O
4
12
LE
11
V
CC
20
O
7
19
D
7
18
D
6
17
SN74LS374
O
6
16
O
5
15
D
5
14
D
4
13
O
4
12
CP
11
1
OE
2
O
0
3
D
0
4
D
1
5
O
1
6
O
2
7
D
2
8
D
3
9
O
3
10
GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
OE
2
O
0
3
D
0
4
D
1
5
O
1
6
O
2
7
D
2
8
D
3
9
O
3
10
GND
LOADING
(Note a)
PIN NAMES
D
0
– D
7
LE
CP
OE
O
0
– O
7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
TRUTH TABLE
LS373
D
n
H
L
X
X
LE
H
H
L
X
OE
L
L
L
H
O
n
H
L
Q
0
Z*
D
n
H
L
X
X
LS374
LE
OE
L
L
H
O
n
H
L
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
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