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SN74LS374N 参数 Datasheet PDF下载

SN74LS374N图片预览
型号: SN74LS374N
PDF下载: 下载PDF文件 查看货源
内容描述: 八路透明锁存器具有三态输出的八路D型触发器具有三态输出 [Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output]
分类和应用: 触发器锁存器逻辑集成电路光电二极管驱动PC
文件页数/大小: 8 页 / 99 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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SN74LS373, SN74LS374
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
LS373
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Maximum Clock Frequency
Propagation Delay,
Data to Output
Clock or Enable
to Output
Output Enable Time
Output Disable Time
12
12
20
18
15
25
12
15
18
18
30
30
28
36
20
25
15
19
20
21
12
15
28
28
28
28
20
25
Min
Typ
Max
Min
35
LS374
Typ
50
Max
Unit
MHz
ns
ns
ns
ns
CL = 5.0 pF
CL = 45 pF
pF,
RL = 667
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
LS373
Symbol
tW
ts
th
Clock Pulse Width
Setup Time
Hold Time
Parameter
Min
15
5.0
20
Max
Min
15
20
0
LS374
Max
Unit
ns
ns
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
SN74LS373
AC WAVEFORMS
tW
LE
1.3 V
ts
Dn
tPLH
OUTPUT
tPHL
th
tW
Figure 1.
OE
tPZL
VOUT
1.3 V
0.5 V
1.3 V
1.3 V
tPLZ
1.3 V
VOL
OE
tPZH
VOUT
1.3 V
1.3 V
tPHZ
1.3 V
VOH
1.3 V
0.5 V
Figure 2.
Figure 3.
http://onsemi.com
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