SN74LS373, SN74LS374
CONNECTION DIAGRAM DIP
(TOP VIEW)
SN74LS373
VCC O7
20
19
D7
18
D6
17
O6
16
O5
15
D5
14
D4
13
O4
12
LE
11
VCC O7
20
19
D7
18
SN74LS374
D6
17
O6
16
O5
15
D5
14
D4
13
O4
12
CP
11
1
OE
2
O0
3
D0
4
D1
5
O1
6
O2
7
D2
8
D3
9
O3
10
GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In Line Package.
1
OE
2
O0
3
D0
4
D1
5
O1
6
O2
7
D2
8
D3
9
O3
10
GND
LOADING
(Note a)
PIN NAMES
D0 - D7
LE
CP
OE
O0 - O7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
TRUTH TABLE
LS373
Dn
H
L
X
X
LE
H
H
L
X
OE
L
L
L
H
On
H
L
Q0
Z*
Dn
H
L
X
X
LS374
LE
OE
L
L
H
On
H
L
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
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