SN74LS164
LOGIC DIAGRAM
1
2
A
D
B
C
D
C
D
C
D
C
D
C
D
C
D
C
D
C
D
CP
MR
V
CC
= PIN 14
GND = PIN 7
= PIN NUMBERS
Q
0
3
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
8
9
Q
1
4
Q
2
5
Q
3
6
Q
4
10
Q
5
11
Q
6
12
Q
7
13
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A or B);
either of these inputs can be used as an active HIGH Enable
for data entry through the other input. An unused input must
be tied HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the logical
AND of the two data inputs (A•B) that existed before the
rising clock edge. A LOW level on the Master Reset (MR)
input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
MODE SELECT — TRUTH TABLE
OPERATING
MODE
Reset (Clear)
Shift
INPUTS
MR
L
H
H
H
H
A
X
I
I
h
h
B
X
I
h
I
h
OUTPUTS
Q
0
L
L
L
L
H
Q
1
–Q
7
L–L
q
0
– q
6
q
0
– q
6
q
0
– q
6
q
0
– q
6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don’t Care
q
n
= Lower case letters indicate the state of the referenced input or output one
q
n
=
set-up time prior to the LOW to HIGH clock transition.
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