SN74LS164
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
14
Q
7
13
Q
6
12
Q
5
11
Q
4
10
MR
9
CP
8
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
A
2
B
3
Q
0
4
Q
1
5
Q
2
6
Q
3
7
GND
LOADING
(Note a)
PIN NAMES
A, B
CP
MR
Q
0
– Q
7
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1
2
8
A
LS164
B
8-BIT SHIFT REGISTER
CP
MR Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
9
3 4
5
6 10 11 12 13
V
CC
= PIN 14
GND = PIN 7
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