NCP1442, NCP1443, NCP1444, NCP1445
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
surface of the chip might be considered to reduce T . A
copper “landing pad” can be connected to ground −
designers are referred to ON Semiconductor applications
note SR006 for more information on properly sizing a
copper area.
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gradient is expressed in manufacturers’ data sheets as q
or junction−to−ambient thermal resistance. The on−chip
,
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Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
junction temperature can be calculated if q , the air
temperature near the surface of the IC, and the on−chip
power dissipation are known.
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T + T )(P q
D JA
)
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A
where:
T = IC or FET junction temperature (°C);
1. In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on−chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on−chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
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T = ambient temperature (°C);
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P = power dissipated by part in question (W);
D
q
= junction−to−ambient thermal resistance (°C/W).
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For ON Semiconductor components, the value for q can
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be found on page 19 of the datasheet, under “Package
Thermal Data.” Note that this value is different for every
package style and every manufacturer. For the NCP144X,
q
varies between 10−50°C/W, depending upon the size of
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the copper pad to which the IC is mounted.
Once the designer has calculated T , the question of
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2. Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
3. Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
whether the NCP144X can be used in an application is
settled. If T exceeds 150°C, the absolute maximum
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allowable junction temperature, the NCP144X is not
suitable for that application.
If T approaches 150°C, the designer should consider
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possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
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