NCP1442, NCP1443, NCP1444, NCP1445
The low frequency pole, f is determined by the error
amplifier output resistance and C1 as:
P1,
−V
OUT
2 V
R
1
P
f
+
P1
200 kW
R1
2pC1R
O
R
IN
NFB
+
The first zero generated by C1 and R1 is:
250 kW
1
f
+
R2
Z1
−
2pC1R1
The phase lead provided by this zero ensures that the loop
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
Negative Error−Amp
Figure 32. Negative Error Amplifier and NFB Pin
It is shown that if R1 is less than 10 k, the deviation from
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
1
f
P
+
2pC R
O LOAD
where:
considered, the possible offset of the output V
in the range of:
varies
OFFSET
C = equivalent output capacitance of the error amplifier
O
≈120pF;
*0.0.5 (R1 ) R2)
R
= load resistance.
LOAD
ǒ
Ǔ* (15 mA R1) v V
OFFSET
R2
0.0.5 (R1 ) R2)
The high frequency pole, f , can be placed at the output
P2
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
v ǒ
Ǔ* (5 mA R1)
R2
VSW Voltage Limit
In the boost topology, V pin maximum voltage is set by
SW
1
f
+
P2
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes:
2pC2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
V
+ V
)V
OUT(MAX)
SW(MAX)
F
should be selected at the midpoint between f and f where
Z1
P2
where:
V = output diode forward voltage.
the phase margin is maximized.
F
In the flyback topology, peak V voltage is governed by:
SW
V
+ V
)(V
CC(MAX)
)V ) N
OUT
SW(MAX)
F
f
P1
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
f
Z1
f
P2
inductance charging stray capacitance between the V and
SW
GND pins. To prevent the voltage at the V
pin from
SW
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
Frequency (LOG)
Figure 31. Bode Plot of the Compensation Network
Shown in Figure 30
the V pin and ground.
SW
Negative Voltage Feedback
Since the negative error amplifier has finite input
impedance as shown in Figure 32, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:
*2.475 (R1 ) R2)
+ ǒ
Ǔ*10 mA R1
*V
OUT
R2
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