NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
8.5 V
Vcc
6.00
8.00
7.5 V
4.00
2.00
Device
Internally
Pulses
0
Startup Period
Figure 14. The Charge/Discharge Cycle Over a 10
mF
V
CC
Capacitor
The protection burst duty−cycle can easily be computed
through the various timing events as portrayed by Figure 16.
Being loaded by the circuit consumption, the voltage on
the V
CC
capacitor goes down. When the DSS controller
detects that V
CC
has reached 7.5 V (VCC
ON
), it activates the
internal current source to bring V
CC
toward 8.5 V and stops
again: a cycle takes place whose low frequency depends on
the V
CC
capacitor and the IC consumption. A 1.0 V ripple
takes place on the V
CC
pin whose average value equals
(VCC
OFF
+ VCC
ON
)/2. Figure 14 portrays a typical
operation of the DSS.
As one can see, the V
CC
capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
reached before V
CC
crosses 7.5 V (otherwise the part enters
the fault condition mode). If we know that
DV
= 1.0 V
and ICC1 (max) is 1.1 mA (for instance we selected an 11
W
device switching at 65 kHz), then the V
CC
capacitor can
suppose that the SMPS needs 10 ms to startup, then we will
calculate C to offer a 15 ms period. As a result, C should be
greater than 20
mF
thus the selection of a 33
mF/16
V
capacitor is appropriate.
Short Circuit Protection
ICC1 · tstartup
(eq. 1)
be calculated using:
C
w
. Let’s
DV
for the presence of the error flag every time V
CC
crosses
VCC
ON
. If the error flag is low (peak limit not active) then
the IC works normally. If the error signal is active, then the
NCP101X immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: V
CC
drops toward ground until it reaches
the so−called latch−off level, where the current source
activates again to attempt a new restart. When the error is
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch−off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short−circuit. Figure 15
shows the corresponding diagram.
Current Sense
Information
4V
FB
Division
Max
Ip
V
CC
+
−
VCC
ON
Signal
To
Latch
Reset
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (Vout is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g. in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
Clamp
Active?
Flag
Figure 15. Simplified NCP101X Short−Circuit
Detection Circuitry
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