NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Tsw
1 V Ripple
Tstart
TLatch
Latch−off
Level
Figure 16. NCP101X Facing a Fault Condition (Vin = 150 Vdc)
The rising slope from the latch−off level up to 8.5 V
is expressed by:
Tstart
+
DV1
· C
. The time during which
Finally,
the IC actually pulses is given by
tsw
+
DV2
· C
.
ICC1
the
latch−off
time
can
be
ICC2
IC1
Vds(t)
toff
Vin
Vr
dt
derived
using the same formula topology:
TLatch
+
DV3
· C
.
From these three definitions, the burst duty−cycle
can be computed:
dc
+
dc
+
DV2
(eq. 3)
.
DV3
DV2
ICC1 ·
ICC1
)
DV1
)
ICC2
IC1
Tsw
(eq. 2)
.
Tstart
)
Tsw
)
TLatch
Feeding
the
ton
Tsw
t
equation with values extracted from the parameter section
gives a typical duty−cycle of 13%, precluding any lethal
thermal runaway while in a fault condition.
DSS Internal Dissipation
Figure 17. A typical drain−ground waveshape
where leakage effects are not accounted for.
The Dynamic Self−Supplied pulls energy out from the
drain pin. In Flyback−based converters, this drain level can
easily go above 600 V peak and thus increase the stress on the
DSS startup source. However, the drain voltage evolves with
time and its period is small compared to that of the DSS. As
a result, the averaged dissipation, excluding capacitive losses,
can be derived by:
PDSS
+
ICC1 ·
t
Vds(t)
u
.
(eq. 4)
.
Figure 17 portrays a typical drain−ground waveshape where
leakage effects have been removed.
By looking at Figure 17, the average result can easily be
derived by additive square area calculation:
t
Vds(t)
u+
Vin · (1
*
d)
)
Vr · toff
Tsw
(eq. 5)
By developing Equation 5, we obtain:
t
Vds(t)
u+
Vin
*
Vin · ton
)
Vr · toff
Tsw
Tsw
(eq. 6)
toff can be expressed by:
toff
+
Ip ·
can be evaluated by:
ton
+
Ip ·
Lp
(eq. 8)
.
Vin
Lp
(eq. 7)
where ton
Vr
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