NBSG72A
VTD0
50 W
50 W
D0
2
2
2
2
D0
2
Q0
Q0
+
D1
D1
50 W
VTD1
50 W
V
CC
Table 2. TRUTH TABLE
V
EE
2
2
SELA
LOW
HIGH
LOW
HIGH
SELB
LOW
LOW
HIGH
HIGH
Q0
D0
D1
D0
D1
Q1
D0
D0
D1
D1
SELA
75 kW
2
Q1
Q1
2
2
SELB
OLS
75 kW
Figure 2. Logic/Block Diagram
Table 3. OUTPUT LEVEL SELECT (OLS)
OLS
Output Amplitude (V
)
OLS Sensitivity
OLS − 75 mV
OLS ± 150 mV
OLS ± 100 mV
OLS ± 75 mV
OLS ± 100 mV
N/A
OUTPP
V
CC
800 mV
200 mV
600 mV
0
V
V
V
− 0.4 V
− 0.8 V
− 1.2 V
(Note 3)
CC
CC
CC
V
EE
400 mV
600 mV
FLOAT
3. When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .
EE
CC
EE
Table 4. INTERFACING OPTIONS
Interfacing Options
CML
Connections
Connect VTD0 and VTD1 to V
CC
LVDS
VTD0 and VTD1 Should Be Left Floating.
AC−COUPLED
Bias VTD0 and VTD1 Inputs within Common Mode Range (VIHCMR)
Standard ECL Termination Techniques
RSECL, PECL, NECL
LVCMOS / LVTTL
The external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V /2 for LVCMOS Inputs.
CC
http://onsemi.com
3
ONSEMI [ ONSEMI ]
