MJD44H11 (NPN) MJD45H11 (PNP)
1
0.7
0.5
0.3
0.2
0.1
0.1
0.07
0.05
0.03
0.02
SINGLE PULSE
0.05
0.02
0.01
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
D = 0.5
0.2
R
qJC(t)
= r(t) R
qJC
R
qJC
= 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
t, TIME (ms)
10
20
30
50
100
200 300
500
1k
Figure 1. Thermal Response
20
IC, COLLECTOR CURRENT (AMP)
10
5
3
2
1
0.5
0.3
0.1
THERMAL LIMIT @ T
C
= 25°C
WIRE BOND LIMIT
dc
5 ms
500
ms
100
ms
1 ms
0.05
0.02
1
5
7 10
20 30
3
50
V
CE
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
70 100
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 2 is based on T
J(pk)
= 150_C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
v
150_C. T
J(pk)
may be calculated from the data in
Figure 1. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
Figure 2. Maximum Forward Bias
Safe Operating Area
T
A
T
C
2.5 25
PD, POWER DISSIPATION (WATTS)
2 20
T
C
1.5 15
1 10
T
A
SURFACE
MOUNT
0.5
0
5
0
25
50
75
100
125
150
T, TEMPERATURE (°C)
Figure 3. Power Derating
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