MC34067, MC33067
Error Amplifier
The minimum frequency is programmed by R
Equation 1:
using
OSC
A fully accessible high performance Error Amplifier is
provided for feedback control of the power supply system.
The Error Amplifier is internally compensated and features
dc open loop gain greater than 70 dB, input offset voltage of
less than 10 mV and a guaranteed minimum gain−bandwidth
product of 2.5 MHz. The input common mode range extends
from 1.5 V to 5.1 V, which includes the reference voltage.
1
t
−
PD
t
−
70 ns
ƒ
(max)
(min)
(eq. 1)
R
=
=
OSC
5.1
0.348 C
C
ȏn
ǒ3.6Ǔ
OSC
OSC
where tPD is the internal propagation delay.
The maximum oscillator frequency is set by the current
through resistor R . The current required to discharge
VFO
Oscillator
Control Current
C
OSC
at the maximum oscillator frequency can be calculated
by Equation 2:
3.1 V
3
5.1 − 3.6
1
ƒ
I
= C
= 1.5C
OSC
I
R
VFO
(max)
(max)
OSC
OSC
6
8
7
Error Amp
Clamp
(eq. 2)
ƒ
(max)
Error Amp Output
The discharge current through R
and can be calculated by Equation 3:
must also be known
OSC
Noninverting Input
Inverting Input
1
Error
Amp
ƒ
(min)
ǒ Ǔ
−
R
C
OSC OSC
5.1 − 3.6
ε ǒ
−
Ǔ
I
=
R
OSC
R
(eq. 3)
OSC
Figure 17. Error Amplifier and Clamp
1
ƒ
R
C
(min) OSC OSC
1.5
=
ε
When the Error Amplifier output is coupled to the I
pin by R
OSC
R
OSC
, as illustrated in Figure 17, it provides the
VFO
Resistor R
can now be calculated by Equation 4:
Oscillator Control Current, I
. The output swing of the
VFO
OSC
Error Amplifier is restricted by a clamp circuit to improve
its transient recovery time.
2.5 − V
EAsat
R
=
(eq. 4)
VFO
−
I
I
R
(max)
OSC
Output Section
One−Shot Timer
The pulse(t ), generated by the Oscillator and One−Shot
OS
The One−Shot is designed to disable both outputs
simultaneously providing a deadtime before either output is
timer is gated to dual totem−pole output drives by the
Steering Flip−Flop shown in Figure 18. Positive transitions
enabled. The One−Shot capacitor (C ) is charged
of t toggle the Flip−Flop, which causes the pulses to
T
OS
concurrently with the oscillator capacitor by transistor Q1,
as shown in Figure 16. The one−shot period begins when the
alternate between Output A and Output B. The flip−flop is
reset by the undervoltage lockout circuit during startup to
guarantee that the first pulse appears at Output A.
oscillator comparator turns off Q1, allowing C to
T
discharge. The period ends when resistor R discharges C
T
T
to the threshold of the One−Shot comparator. The lower
threshold of the One−Shot is 3.6 V. By choosing C , R can
V
CC
T
T
by solved by Equation 5:
t
t
OS
OS
Output A
R
=
=
T
(eq. 5)
5.1
Steering
Flip−Flop
14
13
ȏn
0.348 C
T
C
ǒ3.6Ǔ
T
Power Ground
PWR
GND
Q
T
Errors in the threshold voltage and propagation delays
through the output drivers will affect the One−Shot period.
To guarantee accuracy, the output pulse of the control chip
V
Q
CC
R
is trimmed to within 5% of 250 ns with nominal values of R
T
Output B
and C .
T
12
The outputs of the Oscillator and One−Shot comparators
are OR’d together to produce the pulse t , which drives the
Flip−Flop and output drivers. The output pulse (t ) is
OS
PWR
GND
OS
initiated by the Oscillator and terminated by the One−Shot
comparator. With zero voltage resonant mode converters,
the oscillator discharge time should never be set less than the
one−shot period.
Figure 18. Steering Flip−Flop and Output Drivers
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