MC34067, MC33067
UVLO
Fault
Soft−Start Circuit
The Soft−Start circuit shown in Figure 20 forces the
variable frequency Oscillator to start at the maximum
frequency and ramp downward until regulated by the
feedback control loop. The external capacitor at the
UVLO + Fault
Fault Fault
Comparator Input
R
S
Q
9.0 mA
10
C
terminal is initially discharged by the
Soft−Start
Fault
Latch
UVLO+Fault signal. The low voltage on the capacitor
passes through the Soft−Start Buffer to hold the Error
Amplifier output low. After UVLO+Fault switches to a
logic zero, the soft−start capacitor is charged by a 9.0 mA
current source. The buffer allows the Error Amplifier output
to follow the soft−start capacitor until it is regulated by the
Error Amplifier inputs. The soft−start function is generally
applicable to controllers operating below resonance and can
Error Amp
Clamp
1.0 V
Soft−Start
Buffer
C
Soft−Start
11
6
Ground
be disabled by simply opening the C
terminal.
Soft−Start
Figure 20. Fault Detector and Soft−Start
APPLICATIONS INFORMATION
The MC34067 is specifically designed for zero voltage
The desired resonant frequency for the application circuit
is calculated by Equation 6:
switching (ZVS) quasi−resonant converter (QRC)
applications. The IC is optimized for double−ended
push−pull or bridge type converters operating in continuous
conduction mode. Operation of this type of ZVS with
resonant properties is similar to standard push−pull or bridge
circuits in that the energy is transferred during the transistor
on−time. The difference is that a series resonant tank is
usually introduced to shape the voltage across the power
transistor prior to turn−on. The resonant tank in this
topology is not used to deliver energy to the output as is the
case with zero current switch topologies. When the power
transistor is enabled the voltage across it should already be
zero, yielding minimal switching loss. Figure 21 shows a
timing diagram for a half−bridge ZVS QRC. An application
circuit is shown in Figure 22. The circuit built is a dc to dc
half−bridge converter delivering 75 W to the output from a
48 V source.
When building a zero voltage switch (ZVS) circuit, the
objective is to waveshape the power transistor’s voltage
waveform so that the voltage across the transistor is zero
when the device is turned on. The purpose of the control IC
is to allow a resonant tank to waveshape the voltage across
the power transistor while still maintaining regulation. This
is accomplished by maintaining a fixed deadtime and by
varying the frequency; thus the effective duty cycle is
changed.
1
=
ƒ
(eq. 6)
r
2π
L
2C
L R
In the application circuit, the operating voltage is low and
the value of C versus Drain Voltage is known. Because
OSS
the C
of a MOSFET changes with drain voltage, the
OSS
value of the C is approximated as the average C
of the
R
OSS
MOSFET. For the application circuit the average C
be calculated by Equation 7:
can
OSS
1
2
C
=
(eq. 7)
2 * C
measured at
V
in
R
OSS
The MOSFET chosen fixes C and that L is adjusted to
R
L
achieve the desired resonant frequency.
However, the desired resonant frequency is less critical
than the leakage inductance. Figure 21 shows the primary
current ramping toward its peak value during the resonant
transition. During this time, there is circulating current
flowing through the secondary inductance, which
effectively makes the primary inductance appear shorted.
Therefore, the current through the primary will ramp to its
peak value at a rate controlled by the leakage inductance and
the applied voltage. Energy is not transferred to the
secondary during this stage, because the primary current has
not overcome the circulating current in the secondary. The
larger the leakage inductance, the longer it takes for the
primary current to slew. The practical effect of this is to
lower the duty cycle, thus reducing the operating range.
Primary side resonance can be used with ZVS circuits. In
the application circuit, the elements that make the resonant
tank are the primary leakage inductance of the transformer
(L ) and the average output capacitance (C ) of a power
L
OSS
MOSFET (C ).
R
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