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MC100LVEL01DTG 参数 Datasheet PDF下载

MC100LVEL01DTG图片预览
型号: MC100LVEL01DTG
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V ECL 4输入或/或非 [3.3V ECL 4−Input OR/NOR]
分类和应用: 栅极触发器逻辑集成电路光电二极管
文件页数/大小: 7 页 / 134 K
品牌: ONSEMI [ ONSEMI ]
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MC100LVEL01  
Z = 50 W  
Q
Q
D
D
o
Receiver  
Device  
Driver  
Device  
Z = 50 W  
o
50 W  
50 W  
V
TT  
V
TT  
= V 3.0 V  
CC  
Figure 2. Typical Termination for Output Driver and Device Evaluation  
(See Application Note AND8020/D Termination of ECL Logic Devices.)  
ORDERING INFORMATION  
Device  
MC100LVEL01D  
Package  
Shipping  
SOIC8  
98 Units / Rail  
98 Units / Rail  
MC100LVEL01DG  
SOIC8  
(PbFree)  
MC100LVEL01DR2  
MC100LVEL01DR2G  
SOIC8  
2500 / Tape & Reel  
2500 / Tape & Reel  
SOIC8  
(PbFree)  
MC100LVEL01DT  
MC100LVEL01DTG  
TSSOP8  
100 Units / Rail  
100 Units / Rail  
TSSOP8  
(PbFree)  
MC100LVEL01DTR2  
MC100LVEL01DTR2G  
TSSOP8  
2500 / Tape & Reel  
2500 / Tape & Reel  
TSSOP8  
(PbFree)  
MC100LVEL01MNR4  
MC100LVEL01MNR4G  
DFN8  
1000 / Tape & Reel  
1000 / Tape & Reel  
DFN8  
(PbFree)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
Resource Reference of Application Notes  
AN1405/D  
AN1406/D  
AN1503/D  
AN1504/D  
AN1568/D  
AN1672/D  
AND8001/D  
AND8002/D  
AND8020/D  
AND8066/D  
AND8090/D  
ECL Clock Distribution Techniques  
Designing with PECL (ECL at +5.0 V)  
ECLinPSt I/O SPiCE Modeling Kit  
Metastability and the ECLinPS Family  
Interfacing Between LVDS and ECL  
The ECL Translator Guide  
Odd Number Counters Design  
Marking and Date Codes  
Termination of ECL Logic Devices  
Interfacing with ECLinPS  
AC Characteristics of ECL Devices  
http://onsemi.com  
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