MC10EP101, MC100EP101
D0d D1a D1b D1c D1d D2a D2b D2c
V
V
Q0 Q0
V
D0a D0b D0c
EE
CC
CC
32
31 30
29 28
27 26
25
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
D0c
D0b
D0a
D2d
D3a
1
2
3
4
5
6
7
8
V
24
23
D0d
D1a
CC
Q1
22 D1b
D3b Q1
21
Q2
Q2
Q3
Q3
D1c
V
V
CC
EE
MC10EP101
MC100EP101
MC10EP101
MC100EP101
20
19
D1d
D2a
Q0
Q0
D3c
D3d
18
17
D2b
D2c
V
V
EE
CC
CC
V
CC
V
NC
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
D3d D3c V D3b D3a D2d
NC
V
EE
CC
V
Q1 Q1 Q2 Q2 Q3 Q3 V
CC
CC
Figure 2. 32−Lead QFN Pinout (Top View)
Warning: All V and V pins must be externally connected to
CC
EE
Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
D
D
0a
PIN
FUNCTION
Q
Q
0b
0
0
D
0c
D0a*−D3d*
Q0−Q3, Q0−Q3
ECL Data Inputs
ECL Data Outputs
D
0d
V
Positive Supply
Negative Supply
No Connect
D
D
D
CC
1a
Q
Q
1b
V
1
1
EE
1c
NC
D
1d
EP for QFN−32,
only
The Exposed Pad (EP) on the
QFN−32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat−
sinking conduit. The pad is
D
D
2a
Q
2
2b
D
Q
2
2c
D
2d
electrically connected to V
.
EE
*
Pins will default LOW when left open.
D
3a
3b
Q
Q
D
D
3
3
Table 2. TRUTH TABLE
3c
D
3d
Dna
Dnb
Dnc
Dnd
Qn
Qn
V
EE
L
L
L
L
L
H
L
L
L
L
L
H
X
X
X
H
X
H
X
X
H
X
X
H
X
H
X
X
X
H
H
H
H
H
H
H
Figure 3. Logic Diagram
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