ADM1024
Value and Limit Registers: The results of analog
voltage inputs, temperature, and fan speed
measurements are stored in these registers, along with
their limit values.
Analog Output Register: The code controlling the
analog output DAC is stored in this register.
Chassis Intrusion Clear Register: A signal latched on
the chassis intrusion pin can be cleared by writing to
this register.
Serial Bus Interface
Control of the ADM1024 is carried out via the serial bus.
The ADM1024 is connected to this bus as a slave device,
under the control of a master device, e.g., ICH.
The ADM1024 has a 7-bit serial bus address. When the
device is powered up, it will do so with a default serial bus
address. The 5 MSBs of the address are set to 01011, and the
2 LSBs are determined by the logical states of Pin 1 (NTEST
OUT/ADD). This is a three-state input that can be grounded,
connected to V
CC
, or left open-circuit to give three different
addresses.
Table 5. ADD PIN TRUTH TABLE
ADD Pin
GND
No Connect
V
CC
A1
1
0
0
A0
0
0
1
If ADD is left open-circuit, the default address will be
0101100. ADD is sampled only at powerup, so any changes
made while power is on will have no immediate effect.
The facility to make hardwired changes to A1 and A0
allows the user to avoid conflicts with other devices sharing
the same serial bus, for example, if more than one ADM1024
is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high-to-low
transition on the serial data line SDA while the
serial clock line, SCL, remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition, and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus
an R/W bit, which determines the direction of the
data transfer, i.e., whether data will be written to
or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master will
write to the slave device. If the R/W bit is a 1, the
master will read from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, as a low-to-high transition
when the clock is high may be interpreted as a
STOP signal. The number of data bytes that can be
transmitted over the serial bus in a single Read or
Write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In Write mode, the
master will pull the data line high during the tenth
clock pulse to assert a STOP condition. In Read
mode, the master device will override the
Acknowledge Bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
will then take the data line low during the low
period before the tenth clock pulse, then high
during the tenth clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the case of the ADM1024, write operations contain
either one or two bytes, and read operations contain one byte
and perform the following functions.
To write data to one of the device data registers or read
data from it, the Address Pointer Register must be set so that
the correct data register is addressed, then data can be written
into that register or read from it. The first byte of a write
operation always contains an address that is stored in the
Address Pointer Register. If data is to be written to the
device, the write operation contains a second data byte that
is written to the register selected by the Address Pointer
Register. This is illustrated in Figure 10 The device address
is sent over the bus followed by R/W set to 0. This is
followed by two data bytes. The first data byte is the address
of the internal data register to be written to, which is stored
in the Address Pointer Register. The second data byte is the
data to be written to the internal data register.
When reading data from a register, there are two
possibilities:
1. If the ADM1024’s Address Pointer Register value
is unknown or not the desired value, it is first
necessary to set it to the correct value before data
can be read from the desired data register. This is
done by performing a write to the ADM1024 as
before, but only the data byte containing the
register address is sent, as data is not to be written
to the register. This is shown in Figure 11.
A read operation is then performed consisting of
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