ADM1024
Table 4. ELECTRICAL CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted. (Note 1 and 2))
Parameter
OPEN-DRAIN SERIAL DATABUS OUTPUT (SDA)
Output Low Voltage, V
OL
High Level Output Leakage Current, I
OH
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
Glitch Immunity
DIGITAL INPUT LOGIC LEVELS (ADD, CI, RESET, VID0−VID4, FAN1, FAN2)
(Note 7)
Input High Voltage, V
IH
Input Low Voltage, V
IL
NTEST_IN
Input High Current, I
IH
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
(Note 8)
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU; STA
Start Hold Time, t
HD; STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU; DAT
Data Hold Time, t
HD; DAT
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
−
−
1.3
600
600
1.3
0.6
−
−
100
−
−
−
−
−
−
−
−
−
−
−
−
400
50
−
−
−
−
−
300
300
−
900
kHz
ns
ms
ns
ns
ms
ms
ns
ms
ns
ns
V
IN
= V
CC
V
IN
= 0
–1.0
−
−
−
−
20
−
1.0
−
mA
mA
pF
V
CC
= 2.85 V
−
5.5 V
2.2
−
−
V
V
CC
= 2.85 V
−
5.5 V
V
CC
= 2.85 V
−
5.5 V
2.2
−
−
−
−
0.8
V
V
2.2
−
−
−
−
−
500
100
−
0.8
−
−
V
V
mV
ns
I
OUT
=
−3.0
mA, V
CC
= 2.85 V
−3.60
V
V
OUT
= V
CC
−
−
−
0.1
0.4
100
V
mA
Test Conditions/Comments
Min
Typ
Max
Unit
1. All voltages are measured with respect to GND, unless otherwise specified.
2. Typicals are at T
A
= 25C and represent the most likely parametric norm. Shutdown current typ is measured with V
CC
= 3.3V.
3. TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including
an external series input protection resistor value between 0 kW and 1 kW.
4. Total monitoring cycle time is nominally m
755
ms
+ n
33244
ms,
where m is the number of channels configured as analog inputs, plus 2
for the internal V
CC
measurement and internal temperature sensor, and
n
is the number of channels configured as external temperature
channels (D1 and D2).
5. The total fan count is based on two pulses per revolution of the fan tachometer output.
6. Open−drain digital outputs may have an external pullup resistor connected to a voltage lower or higher than V
CC
(up to 6.5 V absolute maximum).
7. All logic inputs except ADD are tolerant of 5.0 V logic levels, even if V
CC
is less than 5.0 V. ADD is a three-state input that may be connected
to V
CC
, GND, or left open−circuit.
8. Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.2 V for a rising edge.
t
R
t
LOW
SCL
t
F
t
HD:STA
t
HD:STA
SDA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STO
t
BUF
P
S
S
P
Figure 2. Serial Bus Timing Diagram
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