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74HCT14DTR2G 参数 Datasheet PDF下载

74HCT14DTR2G图片预览
型号: 74HCT14DTR2G
PDF下载: 下载PDF文件 查看货源
内容描述: 六角施密特触发器逆变器输入通道兼容输入高性能硅栅CMOS [Hex Schmitt−Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS]
分类和应用: 触发器逻辑集成电路光电二极管
文件页数/大小: 8 页 / 125 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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74HCT14
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
I
Latchup
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Latchup Performance
Oxygen Index: 30%
35%
Human Body Model (Note 1)
Machine Model (Note 2)
Above V
CC
and Below GND at 85_C (Note 3)
SOIC
TSSOP
SOIC
TSSOP
Parameter
(Referenced to GND)
(Referenced to GND)
(Referenced to GND)
Value
*0.5
to
)7.0
*0.5
to V
CC
)0.5
*0.5
to V
CC
)0.5
$20
$25
$25
$50
$50
*65
to
)150
260
)150
125
170
500
450
Level 1
UL 94 V−0 @ 0.125 in
>2000
>200
$300
V
mA
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to EIA/JESD78.
4. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
, V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Parameter
(Referenced to GND)
(Referenced to GND)
Min
4.5
0
*55
Max
5.5
V
CC
)125
(Note 5)
Unit
V
V
_C
ns
5. No Limit when V
I
[
50% V
CC
, I
CC
> 1 mA.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
http://onsemi.com
3