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74HCT08DR2GH 参数 Datasheet PDF下载

74HCT08DR2GH图片预览
型号: 74HCT08DR2GH
PDF下载: 下载PDF文件 查看货源
内容描述: 四2输入与门随着LSTTL兼容输入高性能硅栅CMOS [Quad 2-Input AND Gate With LSTTL−Compatible Inputs High−Performance Silicon−Gate CMOS]
分类和应用: 栅极逻辑集成电路光电二极管
文件页数/大小: 7 页 / 138 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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74HCT08
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output
Voltage
Condition
V
out
= 0.1V
|I
out
|
20mA
V
out
= V
CC
0.1V
|I
out
|
20mA
V
in
= V
IL
|I
out
|
20mA
V
in
= V
IL
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
|
20mA
V
in
= V
IH
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
Additional Quiescent Supply
Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
|I
out
|
4.0mA
|I
out
|
4.0mA
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
Guaranteed Limit
−55
to 25°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
2.0
≤85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
20
≤125°C
2.0
2.0
0.8
0.8
4.4
5.4
3.70
0.1
0.1
0.40
±1.0
40
mA
mA
V
Unit
V
V
V
DI
CC
−55°C
5.5
2.9
25 to 125°C
2.4
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I
CC
+
ΣDI
CC
.
AC CHARACTERISTICS
(C
L
= 50pF, Input t
r
= t
f
= 6ns)
Symbol
t
PLH
,
t
PHL
t
TLH
,
t
THL
C
in
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Maximum Input Capacitance
V
CC
(V)
4.5
4.5
Guaranteed Limit
−55
to 25°C
15
15
10
≤85°C
19
19
10
≤125°C
22
22
10
Unit
ns
ns
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
20
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC 2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
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