MC74HC4046A
Phase Comparator 2
and will cause the output to go high until the VCO leading
This detector is a digital memory network. It consists of
four flip–flops and some gating logic, a three state output
and a phase pulse output as shown in Figure 6. This
comparator acts only on the positive edges of the input
signals and is independent of duty cycle.
edge is seen, potentially for an entire SIG period. This
would cause the VCO to speed up during that time. When
IN
using PC , the output of that phase detector would be
1
disturbed for only the short duration of the noise spike and
would cause less upset.
Phase comparator 2 operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO
output and the signal input positive waveform edges. Figure
8 shows some typical loop waveforms. First assume that
Phase Comparator 3
This is a positive edge–triggered sequential phase
detector using an RS flip–flop as shown in Figure 6. When
the PLL is using this comparator, the loop is controlled by
SIG is leading the COMP . This means that the VCO’s
IN IN
positive signal transitions and the duty factors of SIG and
IN
frequency must be increased to bring its leading edge into
proper phase alignment. Thus the phase detector 2 output is
set high. This will cause the loop filter to charge up the VCO
input, increasing the VCO frequency. Once the leading edge
COMP
IN
are not important. It has some similar characteristics to the
edge sensitive comparator. To see how this detector works,
assume input pulses are applied to the SIG
and
IN
COMP ’s as shown in Figure 9. When the SIG leads the
of the COMP is detected, the output goes TRI–STATE
IN
IN
IN
holding the VCO input at the loop filter voltage. If the VCO
COMP , the flop is set. This will charge the loop filter and
IN
still lags the SIG then the phase detector will again charge
IN
cause the VCO to speed up, bringing the comparator into
up the VCO input for the time between the leading edges of
both waveforms.
phase with the SIG . The phase angle between SIG and
IN IN
COMP varies from 0° to 360° and is 180° at f . The
IN
o
2
If the VCO leads the SIG then when the leading edge of
IN
voltage swing for PC is greater than for PC but
3
the VCO is seen; the output of the phase comparator goes
low. This discharges the loop filter until the leading edge of
consequently has more ripple in the signal to the VCO.
WhennoSIG ispresenttheVCOwillbeforcedtof as
IN
min
max
the SIG is detected at which time the output disables itself
IN
opposed to f
when PC is used.
2
again. This has the effect of slowing down the VCO to again
make the rising edges of both waveforms coincidental.
When the PLL is out of lock, the VCO will be running
The operating characteristics of all three phase
comparators should be compared to the requirements of the
system design and the appropriate one should be used.
either slower or faster than the SIG . If it is running slower
IN
the phase detector will see more SIG rising edges and so
IN
the output of the phase comparator will be high a majority
of the time, raising the VCO’s frequency. Conversely, if the
SIG
IN
COMP
IN
VCO is running faster than the SIG , the output of the
V
CC
IN
PC2
OUT
detector will be low most of the time and the VCO’s output
frequency will be decreased.
GND
HIGH IMPEDANCE OFF–STATE
As one can see, when the PLL is locked, the output of
phase comparator 2 will be disabled except for minor
VCO
IN
PCP
OUT
correctionsat the leading edge of thewaveforms. WhenPC
2
is TRI–STATED, the PCP output is high. This output can be
used to determine when the PLL is in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase difference
between the COMP and the SIG . The lock range of the
Figure 8. Typical Waveforms for PLL Using
Phase Comparator 2
SIG
IN
IN
IN
COMP
IN
PLL is the same as the capture range. Minimal power was
consumed in the loop filter since in lock the detector output
PC3
is a high impedance. When no SIG is present, the detector
OUT
VCO
IN
IN
VCC
GND
will see only VCO leading edges, so the comparator output
will stay low, forcing the VCO to f
Phase comparator 2 is more susceptible to noise, causing
.
min
the PLL to unlock. If a noise pulse is seen on the SIG , the
Figure 9. Typical Waveform for PLL Using
Phase Comparator 3
IN
comparator treats it as another positive edge of the SIG
IN
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