MC74HC4046A
Phase Comparators
All three phase comparators have two inputs, SIG and
outputs of these comparators are essentially standard 74HC
outputs (comparator 2 is TRI–STATEABLE). In normal
IN
COMP . The SIG and COMP have a special DC bias
operation V
and ground voltage levels are fed to the loop
IN
IN
IN
CC
network that enables AC coupling of input signals. If the
signals are not AC coupled, standard 74HC input levels are
required. Both input structures are shown in Figure 6. The
filter. This differs from some phase detectors which supply
a current to the loop filter and should be considered in the
design. (The MC14046 also provides a voltage).
V
CC
V
CC
SIG
IN
14
PC2
OUT
13
V
CC
COMP
3
IN
PCP
1
OUT
PC3
OUT
15
PC1
2
OUT
Figure 6. Logic Diagram for Phase Comparators
Phase Comparator 1
two input signals must be in phase. When the input
frequencyisf ,theVCOinputmustbeV andthephase
detector inputs must be 180 degrees out of phase.
This comparator is a simple XOR gate similar to the
74HC86. Its operation is similar to an overdriven balanced
modulator. To maximize lock range the input frequencies
must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase
detector feeds the loop filter which averages the output
voltage. The frequency range upon which the PLL will lock
onto if initially out of lock is defined as the capture range.
The capture range for phase detector 1 is dependent on the
loop filter design. The capture range can be as large as the
lock range, which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the
VCO input voltage must increase and the phase difference
max CC
SIG
IN
COMP
IN
PC1
OUT
V
CC
VCO
IN
GND
Figure 7. Typical Waveforms for PLL Using
Phase Comparator 1
The XOR is more susceptible to locking onto harmonics
of the SIG than the digital phase detector 2. For instance,
IN
a signal 2 times the VCO frequency results in the same
output duty cycle as a signal equal to the VCO frequency.
The difference is that the output frequency of the 2f example
is twice that of the other example. The loop filter and VCO
range should be designed to prevent locking on to
harmonics.
between COMP and SIG will increase. At an input
IN
IN
frequency equal to f
, the VCO input is at 0 V. This
min
requiresthe phase detector output to be grounded; hence, the
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