74HC373
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
D0
D1
NONINVERTING
OUTPUTS
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LATCH
ENABLE
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
LATCH ENABLE
OUTPUT ENABLE
11
1
FUNCTION TABLE
Inputs
Output
Enable
Latch
Enable
D
H
L
X
X
Output
Q
H
L
No Change
Z
L
H
L
H
L
L
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
Value
46.5
1.5
5.0
0.0075
Units
ea
ns
mW
pJ
http://onsemi.com
2