74HC373
Octal 3−State Non−Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The 74HC373 is identical in pinout to the LS373. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the non−inverting version of the HC533A.
Features
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MARKING
DIAGRAM
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
1
HC
373
ALYW
G
G
•
•
•
•
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Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
This is a Pb−Free Device
HC373
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 0
1
Publication Order Number:
74HC373/D
ONSEMI [ ON SEMICONDUCTOR ]
