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74HC245DTR2G 参数 Datasheet PDF下载

74HC245DTR2G图片预览
型号: 74HC245DTR2G
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相总线收发器 [Octal 3−State Noninverting Bus Transceiver]
分类和应用: 总线驱动器总线收发器逻辑集成电路光电二极管
文件页数/大小: 8 页 / 127 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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74HC245
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
out
= 0.1 V
|I
out
|
v
20
mA
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
I
in
I
OZ
I
CC
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
–55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
V
OH
Minimum High−Level Output
Voltage
V
6.0
4.0
40
40
mA
6. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
TLH
,
t
THL
C
in
C
out
Maximum Propagation Delay,
A to B, B to A
(Figures 1 and 3)
Maximum Propagation Delay,
Direction or Output Enable to A or B
(Figures 2 and 4)
Maximum Propagation Delay,
Output Enable to A or B
(Figures 2 and 4)
Maximum Output Transition Time,
Any Output
(Figures 1 and 3)
Maximum Input Capacitance (Pin 1 or Pin 19)
Maximum Three−State I/O Capacitance
(I/O in High−Impedance State)
Parameter
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
–55 to
25_C
75
55
15
13
110
90
22
19
110
90
22
19
60
23
12
10
10
15
v
85_C
95
70
19
16
140
110
28
24
140
110
28
24
75
27
15
13
10
15
v
125_C
110
80
22
19
165
130
33
28
165
130
33
28
90
32
18
15
10
15
Unit
ns
ns
ns
ns
pF
pF
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
40
C
PD
Power Dissipation Capacitance (Per Transceiver Channel) (Note 8)
pF
2
f + I
8. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
V
CC
. For load considerations, see the ON
CC
Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
4