BelaSigna 200
Two analog outputs designed to drive external amplifiers are also available.
Figure 13: Output Stage
8.3 Clock-Generation Circuitry
BelaSigna 200 operates with two main clock domains: a domain running on the system clock (SYS_CLK) and a domain running on the
main clock (MCLK). SYS_CLK can either be internally generated or externally delivered. It is used to drive all on-chip processors such
as the RCore, the WOLA coprocessor and the IOP. MCLK is generated by division of SYS_CLK and is used to drive all A/D converters,
D/A converters and external interfaces (except SPI, PCM, I2S, and GPIO interfaces). The division factor used to create the desired
MCLK from SYS_CLK is configurable to support external clocks with a wide range of frequencies.
The sampling frequency of all A/D converters and D/A converters also depends on MCLK. When MCLK is 1.28MHz, sampling
frequencies in the interval 10.7kHz to 20kHz can be selected. Sampling frequencies up to 60kHz can be obtained with other MCLK
frequencies.
8.4 Battery Monitor
A programmable on-chip battery monitor is available for power management. The battery monitor works by incrementing a counter
value every time the battery voltage goes below a desired, configurable threshold value. This counter value can be used in an
application-specific power-management algorithm running on the RCore. The RCore can initiate any desired actions in case the battery
hits a predetermined value.
8.5 Multi-Chip Sample Clock Synchronization
BelaSigna 200 allows MCLK synchronization between two or more BelaSigna 200 chips connected in a multi-chip configuration.
Samples on multiple chips occur at the same instant in time. This is useful in applications using microphone arrays where synchronous
sampling is required. The sample clock synchronization is enabled using a control bit and a GPIO assignment that brings all MCLKs
across chips to zero phase at the same instant in time.
Rev. 16 | Page 25 of 43 | www.onsemi.com
ONSEMI [ ONSEMI ]
