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MSM514260ESL-60JS 参数 Datasheet PDF下载

MSM514260ESL-60JS图片预览
型号: MSM514260ESL-60JS
PDF下载: 下载PDF文件 查看货源
内容描述: 262,144字×16位动态RAM :快速页面模式类型 [262,144-Word X 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 14 页 / 181 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDD514260ESL-01  
MSM514260E/ESL  
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization  
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.  
2. The AC characteristics assume t = 5ns.  
T
3.  
V
(Min.) and V (Max.) are reference levels for measuring input timing signals. Transition times  
IH IL  
(t ) are measured between V and V .  
T
IH  
IL  
4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.  
5. Operation within the t  
(Max.) limit ensures that t  
(Max.) can be met.  
RAC  
RCD  
t
(Max.) is specified as a reference point only. If t  
is greater than the specified t  
(Max.)  
(Max.)  
RCD  
RCD  
RCD  
limit, then the access time is controlled by t  
.
CAC  
6. Operation within the t  
(Max.) limit ensures that t  
(Max.) is specified as a reference point only. If t  
(Max.) can be met.  
RAD  
RAC  
RAD  
t
is greater than the specified t  
RAD  
RAD  
limit, then the access time is controlled by t  
.
AA  
7.  
t
(Max.) and t  
(Max.) define the time at which the output achieved the open circuit  
OEZ  
OFF  
condition and are not referenced to output voltage levels.  
8.  
9.  
t
or t  
must be satisfied for a read cycle.  
RRH  
RCH  
t
, t  
, t  
, t  
and t  
are not restrictive operating parameters. They are included in  
CPWD  
WCS CWD RWD AWD  
the data sheet as electrical characteristics only. If t  
t  
(Min.), then the cycle is an early  
WCS  
WCS  
write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.  
If t t (Min.), t t (Min.), t t (Min.) and t t (Min.), then  
CWD  
CWD  
RWD  
RWD  
AWD  
AWD  
CPWD  
CPWD  
the cycle is a read modify write cycle and data out will contain data read from the selected cell; if  
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)  
is indeterminate.  
10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle,  
and to the WE leading edge in an OE control write cycle, or a read modify write cycle.  
11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is  
earlier.  
12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.  
13. tCWL should be satisfied by both UCAS and LCAS.  
14. tCP is determined by the time both UCAS and LCAS are high.  
15. Only SL version.  
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