FEDL9205-03
1
Semiconductor
ML9205-01
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
:
:
:
:
:
:
:
:
specifies 1st column data
(written into CGRAM address 01H)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(11th)
specifies 5th column data
(written into CGRAM address 01H)
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(12th)
specifies 1st column data
(written into CGRAM address 02H)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(16th)
specifies 5th column data
(written into CGRAM address 02H)
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(77th)
specifies 1st column data
(written into CGRAM address 0FH)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(81th)
specifies 5th column data
(written into CGRAM address 0FH)
C4 C9 C14 C19 C24 C29 C34
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(82th)
specifies 1st column data
(CGRAM address 00H is written)
C0 C5 C10 C15 C20 C25 C30
*
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(86th)
specifies 5th column data
(CGRAM address 00H is written)
C4 C9 C14 C19 C24 C29 C34
*
X0 (LSB) to X3 (MSB)
C0 (LSB) to C34 (MSB) : Character pattern data (35 bits: 35 outputs per digit)
: Don't care
: CGRAM addresses (4 bits: 16 characters)
*
19/34