FEDL9203-01
1
Semiconductor
ML9203-xx
Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from
“High” to “Low” is recognized in 8-bit units.
tDOFF
tCSH
CS
CP
B3
B0 B1B2 B3
LSB
B0 B1B2
LSB
B6 B7
MSB
B2 B3
B4
B4 B5 B6 B7
MSB
B4 B5
B0 B1
LSB
B5 B6 B7
MSB
DA
1st byte
2nd byte
2nd byte
Character code data of the
next address
Command and address data
Character code data
When data is written
to DCRAM
Note: When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally
incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Address Transition
1110B
1101B
1100B
1011B
1010B
1111B
0000B
0001B
0010B
0011B
0100B
0101B
0110B
1001B
1000B
0111B
Addresses are in transit from 0000B to 1111B in a loop
while being incremented by one for each transition.(1111B
is followed by 0000B.)
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