FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
• Display data RAM (DRAM) read/write
D7
0
D6
0
D5
D4
D3
D2
D1
D0
8-bit DATA
6-bit DATA
The display data RAM read/write instruction writes and reads display data to and from the liquid crystal display
RAM. Data that is input to the address set by the X and Y address registers is written to or read from this register.
The bit length of display data can be selected by the WLS bit of control register 1. If 6-bit data has been selected,
writing to D7 and D6 is invalid, and if read, their values will always be “0”. D7 is the MSB (D5 in the case of 6-bit
data) and D0 is the LSB.
The X address and Y address should be set immediately before writing or reading display data (either X address or
Y address may be set first). However, in the case of successive writings or readings, only one-time settings of X
address and Y address are required immediately before the writing or reading, in which case X address and Y
address are automatically incremented every time data is written or read (see the description under the heading
“X•Y address Counter Auto Increment.”
The contents of this register will not change even if the RESET pin is pulled to a “L” level.
• X address register (XAD) set
D7
D6
D5
D4
D3
D2
D1
D0
—
XAD
—: don’t care
The X address register set instructions sets the X address for the liquid crystal display RAM.
The address setting range is 0 to 7 (00H to 07H) when 8-bit data is selected with the WLS bit (bit D6) of the control
register 1 (WLS = “0”). In this case, this register starts incrementing the X address from the set value each time
RAM is read or written. When the count value of this register returns to 0 from the maximum value 7, the Y
address is automatically incremented as well. Thereafter, the Y address is counted in a loop fashion from 0 to 7.
The address setting range is 0 to 9 (00H to 09H) when 6-bit data is selected (WLS = “1”). In this case this register
starts incrementing the X address from the set value. When the count value of this register returns to 0 from the
maximum value 9, the Y address is automatically incremented as well. Thereafter, the Y address loops from 0 to 9.
Proper operation is not guaranteed if values outside this range are set.
Writing to bits D7 through D4 is invalid. If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
• Y address register (YAD) set
D7
D6
D5
D4
D3
D2
D1
D0
—
YAD
—: don’t care
The Y address register set instruction sets a Y address of RAM for the liquid crystal display.
The Y address setting range varies according to the setting of the DTY bits (bits D1 and D0) of the control register
1 (described later).
The relation between the internal RAM areas and the display RAM areas is shown in the Table below. RAM areas
that are not displayed can be used as data RAM areas.
This register starts incrementing the Y address from the set value each time RAM is read or written. When the
register count returns to 0 from the maximum value (09H), the X address is also incremented automatically.
Thereafter, the Y address is counted in a loop fashion as shown in the Table below. However, if RAM areas that
are not displayed are used, the X address is not incremented automatically.
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