PEDL9044-03
1
Semiconductor
ML9044-xxA/xxB
Expansion Instruction Codes
The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal processing of the
ML9044 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the
ML9044 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
“0” before sending an expansion instruction code to the ML9044.
1) Arbitrator Display Line Set
RS1
0
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
AS
0
Expansion instruction code:
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
CSR
L
duty
1/9
AS bit
Shift direction
Arbitrator’s common pin
COM9
→
COM1 COM9
L
H
L
→
L
1/9
COM2 COM9, COM1
COM1
→
L
1/12
1/12
1/17
1/17
1/9
COM1 COM12
COM12
COM1
→
COM2 COM12, COM1
L
H
L
→
L
COM1 COM17
COM17
COM1
→
COM2 COM17, COM1
L
H
L
→
H
H
H
H
H
H
COM9 COM1
COM1
→
1/9
H
L
COM8 COM1, COM9
COM9
→
1/12
1/12
1/17
1/17
COM12 COM1
COM1
→
H
L
COM11 COM1, COM12
COM12
COM1
→
COM17 COM1
→
H
COM16 COM1, COM17
COM17
2) Contrast Adjusting Data Write
RS1
RS0
0
R/W
DB7
0
DB6
0
DB5
1
DB4
F4
DB3
F3
DB2
F2
DB1
F1
DB0
F0
0
0
Expansion instruction code:
This instruction writes contrast adjusting data (F4 to F0) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin varies
according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal) and becomes
minimum when it is “00” (hexadecimal).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
39/60
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