PEDL9044-03
1
Semiconductor
ML9044-xxA/xxB
10) Busy Flag/Address Counter Read (Execution time: 1 µs)
RS1
1
RS0
0
R/W
DB7
BF
DB6
O6
DB5
O5
DB4
O4
DB3
O3
DB2
O2
DB1
O1
DB0
O0
1
Instruction code:
The “BF” bit (DB7) of this instruction tells whether the ML9044 is busy in internal operation (BF = “1”) or not
(BF = “0”).
When the “BF” bit is “1”, the ML9044 cannot accept any other instructions. Before inputting a new instruction,
check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9044 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
RS1
1
RS0
1
R/W
DB7
P7
DB6
P6
DB5
P5
DB4
P4
DB3
P3
DB2
P2
DB1
P1
DB0
P0
1
Instruction code:
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a
character pattern (P7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Transfer Mode
Setting instruction (see 3).
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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