¡ Semiconductor
ML9041
Expansion Instruction Codes
The busy status of the ML9041 is rather longer than the cycle time of the CPU, since the internal
processing of the ML9041 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is “1”), the ML9041 executes the Busy Flag Read instruction only.
Therefore, the CPU should ensure that the Busy Flag is “0” before sending an expansion
instruction code to the ML9041.
1) Arbitrator Display Line Set
RS1
0
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
AS
0
Exparsion Instruction codes:
This expansion instruction code sets the Arbitrator display line. The relationship between the
status of this bit and the common outputs is as follows:
CSR duty
AS bit
Shift direction
COM1 Æ COM9
Arbitrator's comon pin
L
L
1/9
1/9
L
H
L
COM9
COM1
COM12
COM1
COM17
COM1
COM1
COM9
COM1
COM12
COM1
COM17
COM2 Æ COM9, COM1
COM1 Æ COM12
L
1/12
1/12
1/17
1/17
1/9
L
H
L
COM2 Æ COM12, COM1
COM1 Æ COM17
L
L
H
L
COM2 Æ COM17, COM1
COM9 Æ COM1
H
H
H
H
H
H
1/9
H
L
COM8 Æ COM1, COM9
COM12 Æ COM1
1/12
1/12
1/17
1/17
H
L
COM11 Æ COM1, COM12
COM17 Æ COM1
H
COM16 Æ COM1, COM17
2) Contrast Adjusting Data Write
RS1
0
RS0
0
R/W
DB7
0
DB6
0
DB5
1
DB4
F4
DB3
F3
DB2
F2
DB1
F1
DB0
F0
0
Exparsion Instraction codes:
This instruction writes contrast adjusting data (F to F ) to the contrast register.
4
0
After contrast adjusting data is written in the register, the potential (VLCD) output to the V pin
5
varies according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal)
and becomes minimum when it is “00” (hexadecimal).
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
38/54
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