FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PIN DESCRIPTIONS
Pin
When
PDNB
= “0”
“L”
“0”
“0”
Symbol
I/O
Description
12.288 MHz clock output
Test control input 1: Normally, input “0”.
Test control input 0: Normally, input “0”.
General-purpose I/O port C [0]
TQFP100 QFP64
1
2
3
4
5
6
7
—
1
2
—
—
3
CLKOUT
TST1
TST0
GPIOC[0]
GPIOC[1]
PCMO
O
I
I
I/O
I/O
O
I
I
I
General-purpose I/O port C [1]
“Hi-z” PCM data output [Open drain output pin]
I
4
PCMI
PCM data input
CLKSEL = ”0”
PCM shift clock input
I
8
5
BCLK
I/O
I/O
CLKSEL = ”1”
“L”
I
PCM shift clock output
CLKSEL = ”0”
PCM synchronous signal 8 kHz input
CLKSEL = ”1”
9
6
SYNC
“L”
PCM synchronous signal 8 kHz output
General-purpose I/O port C[2]
General-purpose I/O port C[3]
Digital power supply
General-purpose I/O port C[4]
General-purpose I/O port C[5]
Transmit buffer DMA access acknowledge signal input
(primary function)
10
11
12
13
14
—
—
7
—
—
GPIOC[2]
GPIOC[3]
DVDD0
GPIOC[4]
GPIOC[5]
I/O
I/O
—
I/O
I/O
I
I
—
I
I
ACK0B/GPIOA[
4]
15
8
I/O
I
General-purpose I/O port A[4] (secondary function) [5
V tolerant pin]
Receive buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A [5] (secondary function) [5 V
tolerant pin]
ACK1B/GPIOA[
5]
16
9
I/O
I
17
18
—
—
GPIOC[6]
GPIOC[7]
I/O
I/O
I
I
General-purpose I/O port C [6]
General-purpose I/O port C [7]
FR0B:(FD_SEL = ”0”)
Transmit buffer frame signal output
DMARQ0B: (FD_SEL = ”1”)
Transmit buffer DMA access request signal
FR1B: (FD_SEL = ”0”)
Receive buffer frame signal output
DMARQ1B: (FD_SEL = ”1”)
Receive buffer DMA access request signal output
Interrupt request output (primary function)
General-purpose I/O port A [6] (secondary function) [5 V
tolerant pin]
FR0B
(DMARQ0B)
19
10
O
”H”
FR1B
(DMARQ1B)
20
21
11
12
O
“H”
“H”
INTB/GPIOA[6]
I/O
22
23
24
25
13
14
15
16
CSB
RDB
WRB
I
I
I
I
I
I
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
DGND0
—
—
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