FEDL7033-02
ML7033
1
Semiconductor
CR18 (Test control)
B7
B6
CH2
LOOP0
B5
CH1
LOOP1
B4
CH1
LOOP0
B3
TEST3
0
B2
TEST2
0
B1
TEST1
0
B0
TEST0
0
CH2
LOOP1
CR18
default
B7, B6
0
0
0
0
… CH2 loop-back test mode select
(B7, B6):
(0, 0) = Loop-back OFF
(0, 1) = Loop-back OFF
(1, 0) = Channel 2 digital loop-back test. PCM data output on the PCMOUT pin during
normal operation is internally looped back through the Receive path via the
PCMIN pin. In digital loop-back test mode, input data on PCMIN pin is ignored,
but PCM data continues to be output on the PCMOUT pin.
(1, 1) = Channel 2 analog loop-back test. Analog signals output on the AOUT2P pin (or the
AOUT2P and AOUT2N pins) are internally looped back to the transmit path
behind a built-in feedback amplifier located after the AIN2P, AIN2N and GSX2
pins. In this mode, the AIN2P and AIN2N input pins are ignored. However, analog
signals continue to be output on the AOUT2P pin (or the AOUT2P and the
AOUT2N pins).
A loop-back test is functional only if XSYNC and RSYNC are from the same clock source.
B5, B4
… CH1 loop-back test mode select
(B5, B4):
(0, 0) = Loop-back OFF
(0, 1) = Loop-back OFF
(1, 0) = Channel 1 digital loop-back test. PCM data is output on the PCMOUT pin in
normal operation is internally looped back through the Receive path via the
PCMIN pin. In loop-back test mode, input data on PCMIN pin is ignored. However,
PCM data can be output on the PCMOUT pin.
(1, 1) = Channel 1 analog loop-back test. Analog signals output on the AOUT1P pin (or
from the AOUT1P and the AOUT1N pins) are internally looped back to the
transmit path via a built-in feedback amplifier located after the AIN1P, AIN1N and
GSX1 pins. In this mode, the AIN1P and AIN1N input pins are ignored. However,
analog signals can be output from the AOUT1P pin (or from the AOUT1P and the
AOUT1N pins).
A loop-back test is functional if XSYNC and RSYNC are from the same clock source.
B3 to B0
… LSI test registers for an LSI manufacturer
The default alternation is prohibited. When a write action is executed for CR18, set all of
these bits to “0”.
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