FEDL7020-02
1
Semiconductor
ML7020
Pin No.
21
Symbol
A1
I/O
I
Description
The address input pin A1 for the processor interface.
22
D0
IO The data input/output pin D0 for the processor interface.
IO The data input/output pin D1 for the processor interface.
IO The data input/output pin D2 for the processor interface.
IO The data input/output pin D3 for the processor interface.
23
D1
24
D2
25
D3
26
CLKOUT
X2
O
O
The 3.579545 MHz oscillator circuit output pin.
27
The pins for connecting a 3.579545 MHz crystal. The capacitors and the
feedback resistor are internally connected to these pins. When inputting an
external clock, connect the input to the X1 pin via a 1000 pF capacitor and leave
the pin X2 open.
28
X1
I
The modem transmit data input pin.
29
30
XD
RD
I
The “1” level corresponds to the mark data and the “0” level corresponds to the
space data.
The modem receive data output pin. The mark and space data are the same as
for XD. A mark is output when no carrier is detected.
O
The pin for outputting the carrier detect signal of the modem or the call progress
tone detector output.
31
32
DETB
SP
O
O
The detection result corresponding to the respective operating mode is output
from this pin. A “0” indicates detection and a “1” indicates non-detection.
The DTMF reception detection output pin.
A “0” indicates detection and a “1” indicates non-detection.
5/19
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