FEDL7020-02
1
Semiconductor
ML7020
PIN DESCRIPTIONS
Pin No.
1
Symbol
VDD
I/O
O
Description
Power supply pin. Connect a +5 V power supply to this pin.
The output pin of the input amplifier 1. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and TI– (3) so as to attenuate
high frequency components above 10 kHz.
2
TIO
The inverting input pin for the input amplifier 1. When the input amplifier 1 is not
used, connect pin TIO (2) to pin TI– (3), and connect pin TI+ (4) to pin SGO.
3
4
TI–
TI+
I
I
The non-inverting input pin for the input amplifier 1.
The output pin for the input amplifier 2. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and LI1– (6) so as to attenuate
high frequency components above 10 kHz.
5
LI1O
O
The inverting input pin for the input amplifier 2. When the input amplifier 2 is not
used, connect pin LI1O (5) and LI1– (6), and connect pin LI+ (7) to pin SGO.
6
7
8
LI1–
LI1+
SWI
I
I
I
The non-inverting input pin for the input amplifier 2.
The input pin for SW3. This pin is connected internally to SGO (9) when SW3 is
to be made ON.
The signal ground output pin for external circuits. A voltage of about VDD/2 is
output from this pin.
9
SGO
LI2O
LI2–
O
O
I
The output pin for the input amplifier 3. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and LI2– (10) so as to attenuate
high frequency components above 10 kHz.
10
11
The inverting input pin for the input amplifier 3.
When the input amplifier 3 is not used, connect pin LI2O (10) and LI2– (11).
The output pin of the output amplifier 1.
12
13
14
TO
LO+
LO–
O
O
O
Can drive a load of 1.2 kΩ or more.
The non-inverting output pin for the output amplifier 2. See Figure 2 for details
of connecting a peripheral circuit.
The inverting output pin of the output amplifier 2. See Figure 2 for details of
connecting a peripheral circuit.
The signal ground output pin for internal circuits. A voltage of about VDD/2 is
output from this pin.
15
16
17
SGC
GND
CSB
O
Connect a 1 µF capacitor between SGC (15) and GND (16).
The ground pin for the LSI. Connect a 0 V input to this pin.
The chip select pin for the processor interface.
I
I
Reading and writing are possible when this input is “0”. Reading and writing are
disabled when this input is “1”.
The read control pin for the processor interface.
Data can be read from the LSI when this pin is “0”.
The write control pin for the processor interface.
Data is written into this LSI at the rising edge of the WR signal.
The address input pin A0 for the processor interface.
18
RDB
19
20
WRB
A0
I
I
4/19
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