FEDL7020-02
1
Semiconductor
ML7020
FUNCTIONAL DESCRIPTION
Description of Processor Interface
• List of Registers
Table 1 List of processor interface registers
A1
0
A0
0
R/W
W
D3
D2
D1
PBG1
D0
PBG3
PBG2
PBG0
MODE0
CPT800
ATT
0
1
R/W
R/W
R/W
R
SW1 CONT
SW3 CONT
SW5 CONT
PBR3
MODE2
SW2 CONT
SW4 CONT
PBR2
MODE1
CPTG ON
MOD-DT ON
PBR1
1
0
1
1
0
0
PBR0
*
*
Data written into the registers other than the register [(A1, A0) = (0,0)] can be read out.
Immediately after switching ON the power, use the LSI only after clearing the control registers
using the power down mode.
• PBG3 to 0/PBR3 to 0
The registers PBG3 to 0 are used for setting the DTMF transmit data.
The registers PBR3 to 0 are used for reading the DTMF receive data.
The output frequency does not change even if the code is changed during transmission.
Table 2 shows the data assignments.
Table 2 DTMF transmit/receive data assignments
D3
D2
D1
D0
Higher group
frequency (Hz)
Lower group
frequency (Hz)
CODE
PBG3/
PBG2/
PBG1/
PBG0/
PBR3
PBR2
PBR1
PBR0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
0
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
#
A
B
C
D
14/19
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